1. Technical Field
This invention is related to the field of integrated circuit implementation, and more particularly to techniques for implementing scannable storage elements.
2. Description of the Related Art
Processors, and other types of integrated circuits, typically include a number of logic circuits composed of interconnected transistors fabricated on a semiconductor substrate. Such logic circuits may be constructed according to a number of different circuit design styles. For example, combinatorial logic may be implemented via a collection of unclocked static complementary metal-oxide semiconductor (CMOS) gates situated between clocked state devices such as flip-flops or latches. Alternatively, depending on design requirements, some combinatorial functions may be implemented via clocked dynamic gates, such as domino logic gates.
For testability, integrated circuits often include scan functionality through which test patterns can be inserted into a circuit and test results can be read out. Scan-based testing may enable a greater degree of test coverage of a given design than functional testing, in that scan-based testing may facilitate direct access to logic that might otherwise require hundreds or thousands of execution cycles to be evaluated through normal integrated circuit operation. In some cases, scan-based testing may allow testing of circuit elements that might be impractical or even impossible to test through functional testing.
However, implementing scan functionality into a circuit typically requires implementing some capability for selecting between normal operating mode data and scan data at the input of at least some gates, in order to provide a path via which scan data may be inserted into a circuit during testing. The additional circuitry needed to implement such a selection may create a performance penalty during normal mode circuit operation.